Table of Contents
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Pin No.
Pin Name
R1
A1
R2
BS
R3
NF/PE5
R4
A0
T1
NF/PE2
T2
NF/PE3
T3
D11
T4
NF/PE4
U1
D15
U2
D0
U3
D3
V1
D14
V2
D1
W1
D2
Y1
D13
Y2
D12
W2
VSSQ
Y3
D5
W3
D4
V3
VDDQ
Y4
D9
W4
D6
V4
D10
U4
VDDQ
Y5
D8
W5
D7
V5
VDDQ
U5
VSSQ
Y6
RD/CASS/FRAME
W6
RD/WR
V6
A2
U6
CKE
Y7
WE1/DQM1
W7
WE0/DQM0/REG
V7
VDD
U7
VSS
Y8
A3
W8
A4
V8
VDDQ
U8
VSSQ
Y9
A5
W9
A6
V9
A7
U9
A17
Y10
CKIO
W10
A8
V10
VDDQ
U10
VSSQ
Y11
A9
W11
A10
I/O
I
Address (SHHA)
O
Bus start
O
To IC107
I
Address (SHHA)
O
To EPG
O
To EPG
O/I
Data (SHHD)
I
From EPG
O/I
Data (SHHD)
O/I
Data (SHHD)
O/I
Data (SHHD)
O/I
Data (SHHD)
O/I
Data (SHHD)
O/I
Data (SHHD)
O/I
Data (SHHD)
O/I
Data (SHHD)
-
IO GND
O/I
Data (SHHD)
O/I
Data (SHHD)
-
IO VDD ( SH-SW3.3V )
O/I
Data (SHHD)
O/I
Data (SHHD)
O/I
Data (SHHD)
-
IO VDD ( SH-SW3.3V )
O/I
Data (SHHD)
O/I
Data (SHHD)
-
IO VDD ( SH-SW3.3V )
-
IO GND
O
Read/CAS signal (To SDRAM)
O
Read/Write (To SDRAM)
I
Address (SHHA)
O
Clock output enable (To SDRAM)
O
D15-D8 select signal
O
D7-D0 select signal/REG signal
-
VDD ( SH-SW1.5VA )
-
GND
I
Address (SHHA)
I
Address (SHHA)
-
IO VDD ( SH-SW3.3V )
-
IO GND
I
Address (SHHA)
I
Address (SHHA)
I
Address (SHHA)
I
Address (SHHA)
O
Clock output (To IC110)
I
Address (SHHA)
-
IO VDD ( SH-SW3.3V )
-
IO GND
I
Address (SHHA)
I
Address (SHHA)
Function
5-5
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